Breaking News

Xilinx adds machine learning optimisation to Vivado to accelerate design cycle – Electronics Weekly

Claiming to be able to reduce design compile times by a factor of five, Xilinx has launched the Vivado ML Editions tool suite. The latest addition to the company’s Vivado tool suite is believed to be the first FPGA EDA tool suite based on machine learning (ML) optimisation algorithms.
In addition to faster compile times, it is claimed to deliver 10% improvements on quality of results (QoR) for complex designs, compared with the Vivado HLx Editions tool.
“Machine learning is the next big leap forward for accelerating the design process and delivering QoR gains,” said Nick Ni, director of marketing, Software and AI Solutions at Xilinx. ” The EDA design tool enables ML-based algorithms that accelerate design closure and its launch continues Xilinx’s drive for machine learning, following the introduction of enhanced Versal AI Edge adaptive compute acceleration platforms (ACAPs) with AI Engine-ML increasing ML by a factor of four, compared with the earlier AI Engine architecture.
<?php echo do_shortcode(‘[inread_parallax slot=”DFP-EW-InRead2-Mobile” width=”300″]’); ?>
#DFP-EW-InRead2-Mobile { display: block!important; } @media only screen and (max-width: 768px) { }
<?php echo do_shortcode(‘[inread_parallax slot=”DFP-EW-InRead2-Mobile” width=”300″]’); ?>
#DFP-EW-InRead2-Mobile { display: block!important; } @media only screen and (max-width: 768px) { }
Vivado ML Editions’ design improves timing and generates QoR suggestions that reduce user analysis to accelerate the closure of designs. The tool also improves collaborative designs with Vivado IP Integrator for modular design, enabling team-based design methodology across multiple sites.
An Abstract Shell allows users to define multiple modules within the system to be compiled incrementally and in parallel, accounting for compilation times that are between five and 17 times reduced, compared to traditional full system compilation, says Xilinx. This feature hides design details outside of the modules, to protect customer IP. This feature is critical for FPGA-as-a-service and value-added system integrators.
Other features in this tool include Dynamic Function eXchange (DFX) which enables more efficient use of silicon resources by loading custom hardware accelerators, dynamically at runtime over-the-air. The adaptability of DFX to load design modules in milliseconds opens up new use cases such as swapping different vision algorithms during processing of a frame, or a genomic analysis swapping different algorithms in real-time when sequencing DNA. 
Vivado ML Editions is available now in a Standard Edition(free of charge) and an Enterprise Edition.

Source: https://www.electronicsweekly.com/news/products/fpga-news/xilinx-adds-machine-learning-optimisation-vivado-accelerate-design-cycle-2021-06/